Mainly Tech projects on Python and Electronic Design Automation.

Sunday, September 16, 2007

On assertions and regular expressions

Text editor is to regular expression as
Waveform is to ... assertion

What I mean is that bump in productivity you get when you've learnt to
use regular expressions with vi/vim/sed/awk/perl/grep... on the unix
command line should be matched by an equal jump in productivity if you
use assertions in your digital design flow.

At the moment, the main digital simulation vendors such as Cadence ncsim, and Mentor questasim allow you to embed or attach assertions to designs that are compiled for simulation, and will automatically extract coverage for these assertions.

What is not so widespread, and what needs to be improved, is the use of interpreted assertions at the command lines of waveform browsers/debugging environments to help navigate waveforms (go to the second write after a read of memory in the range ...),; and to help aggregate displayed waveforms for better understanding of what is shown (highlight any overlap of a write on bus1 with a write on bus2).

I'm currently doing a mind experiment on turning assertions on VCD files, into regular expressions on a string.

- Paddy.


  1. Have you taken a look at
    SystemVerilog assertions?

  2. SVA, yes. I guess I mention PSL, and from my preliminary comparison of syntax I preferred PSL.

    The problem is, that until you use either PSL or SVA in anger, you don't see the limitations of their implementations.



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